RTL & Semiconductor Design
From silicon architecture to production-ready ASIC and FPGA implementations
Requirements
Stage visual
RTL Design
Stage visual
Verification
Stage visual
Implementation
Stage visual
ASIC Design
[Image: ASIC chip layout / photomicrograph]
FPGA Implementation
[Image: FPGA block diagram / resource utilization chart]
Tools & Methodologies
[PLACEHOLDER: Add tool ecosystem comparison matrix - Synopsys, Cadence, Xilinx, Intel tools]
Verilog/VHDL
SystemVerilog
Formal Verification
P&R
STA
DFT
Recent Projects
[Project image]
High-Speed Interface
Project details and outcomes
[Project image]
5G Modem
Project details and outcomes
[Project image]
Power Management
Project details and outcomes